micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 1 micro netw orks an integrated circuit systems compan y iso 9001 registered iso 9001 registered m2005-01 frequency translator description the m2005-01 is a vcso (voltage controlled saw oscillator) based clock generator pll designed for r eference clock frequency translation and jitter attenuation in a high speed data communications system. the device is similar to the m2004-01 but includes a frequency hold-over feature that allows the output frequency to be maintained in the event of a disrupted input reference clock. internal divider ratios are user selectable, and external loop filter components allow tailoring of the pll loop r esponse. inputs, v i : ................................................. -0.5 to v cc +0.5v output, v o : ................................................. -0.5 to v cc +0.5v supply voltage, v cc : ......................................................... 4.6 v storage temperature, t sto : ............................ -45 c to +100 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect product reliability. absolute max ratings integrated saw (surface acoustic wave) delay line output clock frequency up to 700mhz (consult factory for available frequencies) rms jitter <1ps rms (12khz-80mhz) hold-over error +10ppm max single 3.3v supply small 9x9mm smt package includes saw device ideal for oc-48, sdh-12, 10gbe transmit clock features
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 2 micro netw orks an integrated circuit systems compan y m 2005-01 saw dela y li ne p hase shifter vcso vc nvc nop_out op_out op_in nop_in m divider m = 3-1023 mux 0 1 p divider p = 1 or 4 serial / parallel configuration register 6 m5:0 p1 p hase detector loop filter amplifier external loop filter com ponents ref_sel ref_clk0 ref_clk1 fout nfout frequency hold mr 0 1 hold s_data s_clk s_load np_load r loop c loop r post c post c post r loop c loop r post r in r in the internal pll will adjust the vcso output frequency to be m (feedback divider) divided by p (input divider) times the selected input reference clock frequency. note that the ratio of m/p times input frequency must be such that it falls within the ?ock?range of the vcso. the m divider (17-bits) can be programmed for a maximum value of 131,071 and a minimum value of 4. the p divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. the n output divider can be programmed to divide the vcso output frequency by 1, or 4 and provide a 50% output duty cycle. the m2005-01 is serially programmed via a 3 wire interface. figure 1 shows the timing diagram for serial programming. the relationship between the vcso frequency, the m & p dividers, and the input ref_clk is defined as follows: f vcso = f ref_clk x m p when the n output divider is included, the complete relationship for the output frequency is defined as: fout = f vcso =f ref_clk x m nn x p the n1 input can be hard wired to set the n divider to a specific state that will automatically occur during power-up. serial operation occurs when s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output divider when s_load transitions from low to- high. the m divider and n output divide values are latched on the high-to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. when the hold input is asserted the m2005-01 will revert back to the initial accuracy of the vcso and remain at that frequency until the hold signal is returned low. functional block diagram figure 1 low low null null null null n1 n0 m5 m4 m3 m2 m1 m0 s_data s_clk s_load
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 3 micro netw orks an integrated circuit systems compan y functional description loop filter figure 2 table 1. recommended loop filter values the m2005-01 requires the use of an external loop filter via the provided filter pins. due to the differential design, the implementation requires two identical rc filters as shown in figure 2. ref_clk vcso m n fout rloop cloop rpost cpost frequency frequency 19.44mhz 622.0800mhz 32 1 622.0800mhz 5k ? 1mf 50k ? 100pf vc nvc op_out nop_out op_in nop_in rloop rloop cloop cloop rpost rpost cpost cpost
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 4 micro netw orks an integrated circuit systems compan y pin descriptions table 2 pin number name i/o configuration description 1, 2, 3 gnd gnd power supply ground 4, 9 op_in, nop_in analog i/o used for external loop filter. see figure 2. 5, 8 nop_out, op_out analog i/o used for external loop filter. see figure 2 6, 7 nvc, vc input vcso differential control voltage input pair 10, 14, 26 gnd gnd power supply ground 11, 19, 22, 33 vcc power positive supply pins 12 hold input pull - down when high the device operates in digital hold mode. lvcmos / lvttl interface levels. 13 n1 input pull - down determines the output divider value as defined in table 3c. lvcmos / lvttl interface levels. 15, 16 fout, nfout output unterminated differential output, 3.3v lvpecl levels. 17 mr input pull - down logic high resets the reference frequency and n output dividers. logic low enables the outputs. l vcmos / lvttl interface levels. 18 s_clock input pull - down clocks in serial data present at s_data input into the shift register on the rising edge of s_clock. 20 s_data input pull - down shift register serial input. data is sampled on the rising edge of s_clock. 21 s_load input pull - down controls transition of data from shift register into the dividers. lvcmos / lvttl interface levels 23 ref_clk 1 input pull - down input reference clock. lvcmos / lvttl interface levels. 24 ref_clk 0 input pull - down input reference clock. lvcmos / lvttl interface levels. 25 ref_sel input pull - down selects between the different reference clock inputs as the pll reference source. see table 3d. lvcmos / lvttl interface levels. 27, 28, 29, 30, 31 n/c no connection. internal test pins. 32, 34, 35, 36
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 5 micro netw orks an integrated circuit systems compan y table 4 parallel & serial modes function pin characteristics symbol parameter test conditions min typical max units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? table 5a inputs mr np_load m n s_load s_clock s_data conditions hx xx xxx reset, forces outputs low. lh xxl data serial input mode. shift register is loaded with data on s_data on each rising edge of s_clock. lh xx ld at a contents of the shift register are passed to the m divider and n output divider. lh xx l data m divider and n output divider values are latched. lh xx lx xp arallel or serial input do not affect shift registers. lh xxh data s_data passed directly to m divider as it is c locked. note: l = low; h = high; x = don? care; = rising edge transition; = falling edge transition
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 6 micro netw orks an integrated circuit systems compan y table 5b parallel mode function serial mode function table 5c inputs n divider output frequency (mhz) n1 n2 value min max 00 1 311 700 10 4 77.75 175 inputs ref_sel reference 0 ref_clk0 1 ref_clk1 power supply dc characteristics symbol parameter test conditions min typ max units v cc po wer supply voltage 3.135 3.3 3.465 v i cc po wer supply current 162 ma v cc = 3.3v 5%, t a = 0 c to 70 c l vcmos/lvttl dc characteristics symbol parameter test conditions min max units v ih input high ref_sel, s_load, 2 vcc + 0.3 v v oltage s_data, s_clock, n1, mr ref_clk0, ref_clk1 2 vcc + 0.3 v v il input low ref_sel, s_load, s_data, s_clock, -0.3 0.8 v v oltage np_load, mr ref_clk0, ref_clk1 -0.3 1.3 v i ih input high n1, mr, s_clock, s_data, s_load, v dd = v in = 3.465v 150 a current ref_sel, ref_clk0, ref_clk1 i il input low n1, mr, s_clock, s_data, s_load, v dd = 3.465, v in = 0v -5 a current ref_sel, ref_clk0, ref_clk1 v oh output high voltage; note 1 2.6 v v ol output low voltage; note 1 0.5 v note 1: outputs terminated with 50 ? to v cc /2. see parameter measurement section, 3.3v output load test circuit.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 7 micro netw orks an integrated circuit systems compan y symbol parameter test conditions min typ max units f out output frequency 77.75 667 mhz noise single side band 1khz offset -72 dbc/hz phase noise 10khz offset -94 dbc/hz 100khz offset -123 dbc/hz j (t) jitter (rms) 12khz to 20 mhz 0.69 ps odc output duty cycle 50 % t r output rise time fout = 155mhz 20% to 80%, each 300 800 ps t s setup time m, n, to np_load 5 ns s_data to s_clk 5 ns s_clk to s_load 5 ns t h hold time m, n, to np_load 5 ns s_data to s_clk 5 ns s_clk to s_load 5 ns t lock pll lock time 1 ms t pw output pulse width s_load tbd ns f hold initial frequency accuracy stable input clock 10 ppm in digital hold mode selected until entering digital hold input frequency characteristics l vpecl dc characteristics symbol parameter signal min max units v oh output high voltage fout, nfout vcc e 1.4 vcc e 1.0 v v ol output low voltage fout, nfout vcc e 2.0 vcc e 1.7 v v swing p eak-to-peak output voltage swing fout, nfout 0.6 0.85 v note 1: output terminated with 50 1 to v cc e2.v ac characteristics symbol parameter test conditions min max units s_clock 50 v note: output terminated with 50 1 to v cc e2.v f in input frequency ref_clk0, ref_clk1 0.3 166 mhz
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 8 micro netw orks an integrated circuit systems compan y clock inputs and outputs 20% 80% 80% 20% t r t f v swing differential input level input and output rise and fall time parameter measurement information v cmr cross points v pp vcc ndiff_clk diff_clk vee
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 9 micro netw orks an integrated circuit systems compan y odc & t period setup and hold time thold thold tset-up tset-up tset-up s_data s_clock s_load m[5:0] n[1:0] np_load pulse width t period t pw t period odc = parameter measurement information
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2005-01 preliminary specifications 10 micro netw orks an integrated circuit systems compan y o rientati o n ta b [] .354 [ 9.0 ] .200 [ 5.1 ] r .006 [r 0.2 ] .025 [ 0.6 ] pin #1 c # 36 l .041 [ 1.0 ] .007 [ 0.2 ] c c l l #1 0 .354 [ 9.0 ] #2 8 #27 #1 9 #1 8 .110 [ 2.8 ] micro networks an integrated circuit systems company 32 4 clark street worcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 european sales headquarters hertogsingel 20 6214 ad maastricht t he netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 www.micronetworks.com micro networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid us or foreign patents. micro networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. contact your nearest micro networks sales representative office for the latest specifications. mechanical dimensions & pin configuration rev. 4.1 ordering information part number m2005-01 - 622.0800 series model vcso frequency (i.e. 622.0800mhz) pin# designation 1gnd 2gnd 3gnd 4 op_in 5 nop_out 6 nvc 7vc 8 op_out 9 nop_in 10 gnd 11 vdd 12 hold 13 n1 14 gnd 15 fout 16 nfout 17 mr 1. dimensions are in inches, ( ) are in mm. pin# designation 18 s_clock 19 vdd 20 s_data 21 s_load 22 vdd 23 ref_clk1 24 ref_clk0 25 ref_sel 26 gnd 27 n/c 28 n/c 29 n/c 30 n/c 31 n/c 32 n/c 33 vdd 34, 35, 36 n/c a vailable vcso frequencies 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830
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